Istituto di Scienza e Tecnologie dell'Informazione     
Triossi A., Orlando S., Raffaetą A., Fruhwirth T. Compiling CHR to parallel hardware. In: PPDP'12 - 14th Symposium on Principles and Practice of Declarative Programming (Leuven, Belgium, 19-21 September 2012). Proceedings, pp. 173 - 184. ACM, 2012.
This paper investigates the compilation of a committed-choice rule- based language, Constraint Handling Rules (CHR), to specialized hardware circuits. The developed hardware is able to turn the intrin- sic concurrency of the language into parallelism. Rules are applied by a custom executor that handles constraints according to the best degree of parallelism the implemented CHR specification can of- fer. Our framework deploys the target digital circuits through the Field Programmable Gate Array (FPGA) technology, by first com- piling the CHR code fragment into a low level hardware description language. We also discuss the realization of a hybrid CHR inter- preter, consisting of a software component running on a general purpose processor, coupled with a hardware accelerator. The latter unburdens the processor by executing in parallel the most computa- tional intensive CHR rules directly compiled in hardware. Finally the performance of a prototype system is evaluated by time effi- ciency measures.
URL: http://dl.acm.org/ft_gateway.cfm?id=2370798&ftid=1290668&dwn=1&CFID=270343077&CFTOKEN=81034639
DOI: http://dx.doi.org/10.1145/2370776.2370798
Subject CHR
Hardware acceleration
D.3.4 Processors

Icona documento 1) Download Document PDF

Icona documento Open access Icona documento Restricted Icona documento Private


Per ulteriori informazioni, contattare: Librarian http://puma.isti.cnr.it

Valid HTML 4.0 Transitional