Istituto di Scienza e Tecnologie dell'Informazione     
Caruso A., Chessa S., Maestrini P. Comparison-based diagnosis of VLSI wafers. In: DDECS 2000 - 3rd Workshop on Design and Diagnostics of Electronic Circuits and Systems (Smolenice Castle, Slovakia, 5-7 2000). Proceedings, pp. 227 - 232. IEEE, 2000.
We present a methodology, based on the theory system-level diagnosis, to execute the wafer,scale test of fCs. With the new methodology, ail fe's on the wafer undergo an intensive test before they are cut, bonded and packaged. The tests are executed by means of comparisons of adjacent ICs, and the faulty ICs are identified by a diagnosis algorithm which provides correct and almost complete identification of good ICs under realistic fault situations. The paper considers different implementations comparison logic and discusses their consistency with the standard diagnostic models.
Subject System-Level Diagnosis
Comparison model
Wafer-scale rest
Built-in self-test
VLSI testing

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