PUMA
Istituto di Scienza e Tecnologie dell'Informazione     
Olariu S., Pinotti M. C., Zheng S. An optimal hardware-algorithm for sorting using a fixed-size parallel sorting device. 2000.
 
 
Abstract
(English)
We present a hardware-algorithm for sorting N elements using either a p-sorter or a sorting network of fixed I/O size p while strictly enforcing conflict-free memory accesses. To the best of our knowledge, this is the first realistic design that achieves optimal time performance, running in N logNp log p time for all ranges of N. Our result completely resolves the problem of designing an implementable, time-optimal algorithm for sorting N elements using a p-sorter. More importantly, however, our result shows that, in order to achieve optimal time performance, all that is needed is a sorting network of depth Olog2 p such as, for example, Batcher's classic bitonic sorting network.
Subject Special-purpose architectures
hardware-algorithms
sorting networks
columnsort
VLSI
C.3 special purpose and application based systems


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