Istituto di Scienza e Tecnologie dell'Informazione     
Sallay B., Maestrini P., Santi P. Wafer-scale diagnosis tolerating comparator faults. In: IEE Proceedings-Computers and Digital Techniques, vol. 146 (4) pp. 211 - 215. 1999.
Abstract: A promising application of comparison-based system-level diagnosis is the testing of VLSI chips during manufacture. However, existing comparison models essentially overlook the test invalidation owing to the physical faults in the comparators. A comparison model is proposed that takes into account faults affecting the comparators and the syndrome generation circuitry. A comparator test session is described that is capable of detecting any combination of stuck-at faults in the diagnostic-circuitry. This test requires units on the wafer to use independent test inputs which can be satisfied at a small wafer design cost.

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