Istituto di Scienza e Tecnologie dell'Informazione     
De Bernardinis F., Roncella R., Saletti R., Terreni P., Bertini G. An efficient VLSI architecture for real-time additive synthesis of musical signals. 1999.
This paper presents a new architecture for the hardware implementation of additive synthesis for high-quality musical sound generation. A marginally stable second-order infiniteimpulse- response filter is used to generate each sinusoid, the frequency, amplitude, and phase of which can independently be specified. A chip has been designed with a bit-level systolic array approach. It is capable of performing 1200 sinusoid real-time synthesis. Furthermore, it is possible to connect up to 11 chips, to achieve an outstanding 13 200 sinusoid synthesis. Two completely independent output channels are available as 20-b streams. The system is clocked at 60 MHz when working with a 44.1-kHz sampling rate. The integrated circuit is designed in a 0.5-m CMOS technology and has a core area of approximately 19 mm2
Subject Additive synthesis
bit-level systolic arrays
IIR marginally stable filters
musical synthesis algorithms
real-time musical synthesis
sinusoid generation
systolic architectures

Icona documento 1) Download Document PDF

Icona documento Open access Icona documento Restricted Icona documento Private


Per ulteriori informazioni, contattare: Librarian http://puma.isti.cnr.it

Valid HTML 4.0 Transitional