Istituto di Scienza e Tecnologie dell'Informazione     
Alia G., Martinelli E. A fast digital circuit for iterative additions in HNS. Internal note IEI-B4-31, 1994.
Repeated modular additions and overflow detection are practicable in Hybrid Number Systems. In this paper, an adding, overflow-detecting procedure is described and evaluated by statistical methods; a circuit is proposed allowing a mean addition time less than 8.9 gate delays for numbers having a magnitude order normally distributed in [-2^33, 2^33-1].
Subject computational complexity
combinational problems
computer arithmetic
weighted and residue number systems
overflow detection
fast accumulator
B.2 Arithmetic and logic structures

Icona documento 1) Download Document PDF

Icona documento Open access Icona documento Restricted Icona documento Private


Per ulteriori informazioni, contattare: Librarian http://puma.isti.cnr.it

Valid HTML 4.0 Transitional