Istituto di Scienza e Tecnologie dell'Informazione     
Codenotti B., Tamassia R. A network flow approach to the reconfiguration of VLSI arrays. In: IEEE Transactions on Computers, vol. 40 (1) pp. 118 - 121. IEEE, 1991.
We present a new technique for reconfiguring a two dimensional VLSI array with faulty cells and compare it to existing ones. Using a network flow model of the problem, we provide an algorithm for connecting the functional cells of the array so that they simulate a fault-free array of smaller size. The interconnection wires are routed inside horizontal and vertical channels according to the Manhattan model. Experimental results indicate that our algorithm has a good performance in practice.
Subject Fault-tolerant system
network flow
systolic arrays
wafer scale integration
wire length

Icona documento 1) Download Document PDF

Icona documento Open access Icona documento Restricted Icona documento Private


Per ulteriori informazioni, contattare: Librarian http://puma.isti.cnr.it

Valid HTML 4.0 Transitional