PUMA
Istituto di Scienza e Tecnologie dell'Informazione     
Lopriore L. Virtual address cache with no reverse address buffering. Progetto finalizzato 'Materiali e dispositivi per l'elettronica a stato solido'. Internal note IEI-B4-46, 1987.
 
 
Abstract
(English)
A virtual address cache memory, whose operation is controlled explicitly by software, is presented. Ad-hoc hardware mechanisms, including new machine instructions and a new operand addressing mode, reduce the complexity of cache management logic in favour of the capacity of the cache, and solve the major problem of virtual address cache organization: two or more virtual addresses mapping into the same real address.
Subject


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