Istituto di Scienza e Tecnologie dell'Informazione     
Alia G., Barsi F., Martinelli E. A fast near optimum VLSI implementation of FFT using residue number systems. In: Integration, The VLSI Journal, vol. 2 article n. 133. 1984.
Many FFT processor designs have been proposed, most of which have been limited by hardware costs when a large number of points is to be processed. In recent years, VLSI technology modified design methodology and determined a reduction of costs. The scope of this work is to present a fast near optimum VLSI architecture for solving an N-point FFT which exhibits T= θ(log log N) and AT= (N1ogN log log N). Main features are: very high parallelism, proper communication parallelism, residue arithmetic, table look-up techniques and pipeline of data. Moreover, it will be shown that design performance does not depend on the input and output data representation (residue or weighted notation).
Subject VLSI Complexity
Residue number system
Fast Fourier Transform
Parallel Processing

Icona documento 1) Download Document PDF

Icona documento Open access Icona documento Restricted Icona documento Private


Per ulteriori informazioni, contattare: Librarian http://puma.isti.cnr.it

Valid HTML 4.0 Transitional