Istituto di Scienza e Tecnologie dell'Informazione     
Alia G., Ciompi P., Martinelli E., Bernardini F. The nucleus of a three-valued functional simulator for logic verification: description and performance experiments. In: Digital Processes, vol. 6 pp. 111 - 126. Georgi Publishing Company, 1980.
The advent of very complex integrated circuits and their wide diffusion has made, in recent years, the use of three-valued gate-level logic simulators highly inefficient, or rather impossible , in terms of memory and time requirements, when large networks must be simulated. The main reason for the weakness of these simulators is the type of internal device models which they handle. These models are the basic gates AND, OR, NOT. etc., and, at most, some more complex elcments as flip-flops. The solution to the problem of an efficient simulation consists essentially in developing functional internal device models. Concepts or primitives and test blocks in functional modelling were discussed by the authors in a previous work. In this paper some primitives are briefly recalled and a more efficient procedure for test biocks is introduced. Simulation experiments on a nucleus of a logic simulator which handles internal models implementing the concepts of primitives and test bIocks are also presented and discussed showing that these models make the slmulator more effective than gate level simulators.
Subject digital circuits
functional simulation
logic verification
three-valued coding
internal device models

Icona documento 1) Download Document PDF

Icona documento Open access Icona documento Restricted Icona documento Private


Per ulteriori informazioni, contattare: Librarian http://puma.isti.cnr.it

Valid HTML 4.0 Transitional